In the field of integrated circuit design and fabrication, and in particular the field of microcontroller unit (MCU) design and fabrication, test throughput and test cost are highly dependent on the number of devices that can be tested in parallel. This is true for both packaged final testing and also for wafer level ‘Known Good Die’ (KGD) flow testing. The major factors that limit the number of devices that are able to be tested in parallel include:                the number of tester channels and resources available; and        the number of package contacts (hereinafter referred to simply as ‘pins’) on each device that need to be coupled to the tester channels and resources.        
Developments in design for test techniques have reduced the number of tests that require every pin on a device to be coupled to a tester channel/resource. However, a small number of tests still require large numbers of pins to be coupled to tester channels/resources, thereby limiting the number of devices that can be tested in parallel. Examples of such tests include Zero Defects tests on all I/O pins such as:                I/O pad leakage tests;        digital input tests (Vil/Vih/Hysteresis)        drive strength (Ioh/Voh/Iol/Vol) tests;        etc.        
Accordingly, there is a continual drive to improve testing techniques to reduce the number of pins required to be coupled to tester channels/resources during such tests, and thus that increase the number of devices that are able to be tested in parallel using the same tester configuration.